Senior ASIC Digital Designer
MonoLets is working on a ground-breaking technology that will enable millions of sensors to collect and send data to the cloud, enabling new use cases currently not possible. MonoLets is built on DARPA research done at UC Berkeley, and has already been successfully piloted with large Enterprises in the field.
MonoLets is looking for a strong ASIC digital design engineer to help take MonoLets proprietary technology into a finished product ready for market. It will involve working on complex engineering problems with wireless-mesh networks, your impact will be critical to the development of this new technology, and enabling a fully connected world of sensors. This is a unique opportunity to work on cutting edge technology, and be part of a high potential startup that could revolutionize the way real-time data is collected around the world. If that sounds exciting then get in touch now and become one of our founding engineers!
• Continue development of MonoLets cutting edge proprietary chip technology
• Design, deploy, debug and test the RTL of the digital system
• Specification for digital portions of integrated circuits and systems
• Working with analog and system IC designers to understand top-level requirements of the digital components of a mixed-signal chip
• Develop RTL to execute required digital functions
• Full digital flow, from functional requirements to layout, and eventually tape-out
• Writing test benches for verification and functional validation
• Define bench-top test plans and verify performance and functionality
• Test and debug chips after they return from fabrication.
• Work closely with the founding team to develop the first product to market and have a lot of input into its design and roadmap
• BS (Masters or Ph.D. preferred) with 5+ yrs. related experience
• Significant experience in digital description: Verilog / VHDL
• Experience with one scripting language (TCL, Python, Perl, Shell scripts)
• System design and simulation using C/MATLAB / Verilog with an emphasis on digital/analog boundary
• Experience with mixed-signal simulations, Verilog-AMS test benches
• Understanding of digital flow – RTL simulation and verification, logic synthesis, timing and power analysis, back annotation and verification, and functional equivalence checking
• Experience with P&R
• Significant familiarity with low-power logic synthesis
• Experience with Synopsys or Cadence digital tool flow
• Experience with mixed-signal design and verification
• Working experience with oscilloscopes, FPGAs, microcontrollers, signal generators for validation and testing of digital and mixed-signal designs
• Experience with digital design fundamentals.
• Experience with emulation on FPGA with respect to System and RTL verification
• Embedded software, firmware and hardware interaction
• Experience with SOC bus fabric design
• Experience with IC bring-up.